Improving FPGA Performance and Area Using an Adaptive Logic Module
2004
This paper proposes a new adaptable FPGA logic element based on fracturable 6-LUTs, which fundamentally alters the longstanding belief that a 4-LUT is the most efficient area/delay tradeoff. We will describe theory and benchmarking results showing a 15% performance increase with 12% area de- crease vs. a standard BLE4. The ALM structure is one of a number of archi- tectural improvements giving Altera's 90nm Stratix II architecture a 50% per- formance advantage over its 130nm Stratix predecessor.
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