Thermal Placement Optimization of Stacked Chips

The thermal placement optimization of stacked chips is proposed in this paper. The paper presents the method to decrease the highest temperature and achieve uniform thermal field distribution. Thermal placement optimization methods of stack chips are proposed in this paper, which is based on the partheno-genetic algorithm and the particle swarm optimization with simulated annealing respectively. Compared with the particle swarm optimization, the optimized method based on the partheno-genetic algorithm obviously performed better both in convergence speed and temperature drop scope. To demonstrate the effectiveness of the obtained optimization program, ANSYS, a finite element analysis tool (FEA), is carried out to assess the thermal field distribution of the optimization placement in stacked chips. The results of the simulation show that the thermal field distribution of the optimization chips placement is in good accord with the FEA tools.