Limits to performance spread tuning using adaptive voltage and body biasing

We examine technology constraints on tuning active power and delay using adaptive voltage scaling (AVS) and adaptive body biasing (ABB) design techniques. To serve this purpose, a test circuit was fabricated in a 90 nm triple-well low-power CMOS technology. The presented analysis is based on a ring oscillator running at 488 MHz and a circular shift register with 8 K flip-flops and 50 K gates. Measurement results indicate that it is possible to reach 24.4/spl times/ power savings by 6.1/spl times/ frequency downscaling using AVS, /spl plusmn/24% power and /spl plusmn/22% frequency tuning at nominal conditions using ABB only, 127/spl times/ power savings with 37.4/spl times/ frequency downscaling by combining AVS and ABB.