A family of robust DMOS devices for automotive applications

This paper presents different methodologies to optimize devices of smart power technologies for robustness consideration. A split gate concept is used to improve the flatness of Id-Vd curves of the nVDMOS by maintaining the Intrinsic MOS in a stable operating regime. The split gate is also used to increase the BVdss of the pLDMOS. An additional buffer at the end of the drift region of the nLDMOS helps extending the SOA limits due to a controlled positive differential resistor branch.