Modeling and Design of High Bandwidth Feedback Loop for dv/dt Control in CMOS AGD for GaN

The objective of this work is to show the intrinsic limitations of a CMOS technology for the realization of an Active Gate Driver (AGD) with an active dv/dt control loop. Due to a theoretical study using first order models of CMOS submicron transistors, the main equations providing the link between feedback loop bandwidth and specific technology parameters are obtained. This optimization study allows us to determine the theoretical limits in terms of bandwidth and silicon area. Then, it becomes possible to determine the most appropriate switching control method to implement depending on the application requirements (high efficiency, low EMI), i.e. active feedback with adjustable gain, while ensuring suitable time delays. A feedback loop bandwidth of 1. 59GHz using a 1pF integrated capacitor to address a switching speed of 175V/ns is demonstrated. Experimental results and simulations using accurate technology models confirm the theory.