Design and analysis of low power open core protocol compliant interface using VHDL

The necessity of Intellectual Properties (IP) reuse to shorten the design time and the complexity makes the large scale System On Chip (SoC) more challenging. An efficient bus protocol for the core communication between IP block is OCP. Open Core Protocol (OCP) defines the only non-proprietary, openly licensed, core centric protocol with high-performance, bus-independent interface between IP cores that reduces design time, design risk, and manufacturing costs and promote IP core reusability for SOC designs. Bus Bridge interconnects other bus standard to OCP. This paper focus on the design and implementation of Bus Bridge using OCP master and I2C slave protocol. I2C is a simple bi-directional 2-wire bus for efficient inter-IC control. The developed FSM's for OCP and I2C were implemented using VHDL and the synthesis is done using Xilinx ISE 10.1.