Data processing unit provided with a plurality of on-chip memory bus

PURPOSE: To section a 2nd memory location flexibly into data and program storages by addressing the 2nd memory location with an address equivalent to an object address in the case of writing a content of a 1st memory location to the 2nd memory location. CONSTITUTION: Data 30 are received on a memory bus 30 in response to an address signal given from a logic arithmetic unit (CPU) 12 on a memory bus 30 and an address signal and a data signal are communicated via a direct memory access (DMA) bus 38 connecting to memories 16, 18, 20. A DMA controller 22 is connected to the DMA bus 38 and reads contents of the 1st memories 16,18 addressable by an address equivalent to a source address and writes contents of location of the 1st memories 16, 18 to a location of t 2nd memory 20. In this case, the location of the 2nd memory 20 is addressed by an address equivalent to an object address.