Development and Result Verification of a Multi-Bit Binary Parallel-Prefix Adder-Subtractor

Binary adder-subtractors (AS) are widely used in operating devices such as arithmetic-logic units, floating-point units, memory-addressing units and other arithmetic devices of all modern microprocessors. Today, much attention focuses to the performance of the operating devices because speed is one of the most important indicators for users. Therefore, the development of an efficient AS aimed at increasing the performance of the operating units of all modern microprocessors is an importance.In this work the development of a parallel-prefix AS (PPAS) based on the modified parallel-prefix adder is proposed for high speed addition and subtraction of two signed multi-bit binary numbers. The comparison of the proposed PPAS and the other existing AS is performed by the circuit occupied area and critical delay. As a result, for 8, 16, 32 and 64-bit input operands, the proposed PPAS has advantage of the critical delay compared to other existing AS and also reduces the circuit area compared to AS based on Kogge-Stone adder. Additionally, a digital circuit is developed to verify the results of the proposed PPAS, when performing operations with all possible values of input operands. Modeling of the presented devices is performed in the Altera Quartus-II environment. The reliability of all results of the proposed PPAS has been practically confirmed on Altera DE-1 board with FPGA Cyclone-II chip EP2C20F484C7.