Transient Overshoot of Sub-10nm Bulk FinFET ESD Diodes with S/D Epitaxy Stressor

New process options in CMOS technology scaling often result in degradation of ESD device performance. TCAD simulations bring an in-depth look at the impact of S/D epitaxy process options with channel strain engineering on CDM-time domain turn-on transient overshoot of ESD diodes in next generation bulk FinFET and GAA technologies.