Phase I Upgrade of the Readout System of the Vertex Detector at the LHCb Experiment

This article describes the high-speed system designed to meet the challenging requirements for the readout of the new pixel VErtex LOcator (VELO) of the upgraded LHCb experiment. All elements of the electronics readout chain will be renewed to cope with the requirement of ~40-MHz full-event readout rate. The pixel sensors will be equipped with VeloPix ASICs and placed at ~5 mm from the Large Hadron Collider (LHC) beams in a secondary vacuum tank in an extremely high and nonhomogeneous radiation environment. The front-end (FE) ASICs with the highest occupancy will have to cope with pixel-hit rates above ~900 Mhits/s using up to four 5.13-Gb/s data readout links. Each module comprises six VeloPix ASICs, wire-bonded to two FE hybrid boards, while a third hybrid will employ a GBTx ASIC as the control interface. High-speed data will reach the wall of the vacuum chamber through low-mass flexible copper tapes. A custom board routes the signals outside the vacuum tank. On the air side, an optical and power board converts the electrical high-speed signals into optical signals for transmission from the underground cavern to the off-detector electronics that process data and send them to a farm of computers for further analysis. Several tests allowing the validation of the system are described here with special emphasis on a test with proton beams that confirms the correct operation of the whole readout hardware.