Integrated device and process technology for sub-70nm low power DRAM

A novel process technology for 70nm DRAM was for the first time developed. ArF lithography with lithography friendly layout and highly selective etching process were used for patterning of critical layers. A novel gap-fill technology using spin coating oxide was used for STI and ILD processes. Metal tungsten on dual poly gate and dual gate oxide with plasma nitridation process was used for the performance of peripheral transistors. Bar type bit line contact was used to increase the transistor current about 10%. MIM cell capacitor was developed with buried-OCS scheme and 15/spl Aring/ equivalent Tox and 1fA leakage was confirmed.