Method for estimating programming condition of anti-fuse FPGA (field-programmable gate array)

The invention discloses a method for estimating the programming condition of an anti-fuse FPGA (field-programmable gate array). The method comprises the following steps: dividing a wafer for bearing the anti-fuse FPGA into a plurality of regions; respectively implanting a plurality of anti-fuse devices for testing in the regions; applying a testing voltage to an upper electrode and a lower electrode of each anti-fuse device for testing and programming for each anti-fuse device for testing; acquiring estimation resistance values of intermediate medium layers of the programmed anti-fuse devices for testing in different regions and comparing the estimation resistance values with a preset reference resistance value so as to determine FPGA function normal ratios corresponding to the different regions; according to the actual condition, estimating the programming condition that the anti-fuse FPGA programs a region to be selected. According to the method, by estimating the programming condition of the anti-fuse FPGA, not only can product quality be greatly improved and reliability of the product is ensured, but also development cost can be reduced.