Multi-step Word-line Control Technology in Hierarchical Cell Architecture for Scaled-down High-density SRAMs

A new hierarchical cell SRAM architecture, combined with a multi-step word-line control technology, has been developed to overcome rapid increase in random variability with no area-penalty. A 40nm-node 0.248 µm2-cell SRAM using a single power supply has been successfully fabricated, pushing up bit-density to 2.98Mb/mm2.