Gate-Length Dependence of Vertical GaSb Nanowire p-MOSFETs on Si

The effect of gate-length variation on key transistor metrics for vertical nanowire p-type GaSb metal–oxide–semiconductor field-effect transistors (MOSFETs) are demonstrated using a gate-last process. The new fabrication method enables short gate-lengths ( ${L}_{g} =40$ nm) and allows for selective digital etching of the channel region. Extraction of material properties as well as contact resistance are obtained by systematically varying the gate-length. The fabricated transistors show excellent modulation properties with a maximum ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}} =700$ ( ${V}_{GS} = -0.5$ V) as well as peak transconductance of $50~\mu \text{S}/\mu \text{m}$ with a linear subthreshold swing of 224 mV/dec.