Placement algorithms for CMOS cell synthesis

Heuristic placement algorithms for the layout synthesis of CMOS logic cells are described. The techniques are not restricted to fully complimentary CMOS, and focus on a novel strategy for FET pair ordering which takes advantage of splitting wide FETs to eliminate diffusion gaps. These algorithms are applicable to strip-based layout synthesis from transistor netlists. Existing CMOS cell synthesis systems neither fully include the costs nor utilize the benefits of FET splitting. The system described does this, in some cases results in an area saving. In general, it trades diffusion gaps for useful FETs. Since some technologies penalize diffusion gaps heavily, and others, such as sea-of-gates, forbid them altogether, such a tradeoff seems increasingly appropriate. >