Smart-Redundancy: an Alternative SEU/SET Mitigation Method for FPGAs

Field Programmable Gate Arrays (FPGAs) reconfigurability is a key asset for many critical applications. State- of-the-art Radiation-Hardening (Rad-Hard) methods for FPGAs consist of triplicating the logic, reinforcing the memories, and bitstream scrubbing with partial reconfiguration. These methods involve a 3× reduction of Maximal Design Capacity (MDC) and an average Time-In-Error (TIE) proportional to design sizes. In this paper, we propose an alternative: Smart-Redundancy (SR), a new method based on the detection of possible events via process and hardware modifications. Thanks to integrated particle sensors, only dual redundancy is required. Results show up to 33.33% improvement in MDC over actual Rad-Hard methods, and an average TIE decrease of at least 10,000× compared to bitstream's scrubbing, at a cost of 41.08% in area using a commercial 40nm technology node.