A Programmable Fully-Integrated GPS receiver in 0.18 μm CMOS with Test Circuits

A 0.18 μm single chip GPS receiver with 19.5 mA power consumption is implemented in 6.5 mm 2 . A serial input digital control with additional testing structure not adding more than 4% to the Si area are used to the actual RF circuits in case of problems minimizing the number of Si runs.