Design Tradeoffs and Predistortion of Digital Cartesian RF-Power-DAC Transmitters

Digital RF transmitter architectures offer several advantages over conventional analog transmitters, including reduced area, reconfigurability, compatibility with scaling, and the ability to use highly efficient switching-class power amplifiers (PAs). However, the nonlinear transfer functions from the switch conductance to the output RF amplitude and phase of these switching-class PAs and the inherent interaction between I and Q paths in digital Cartesian architectures necessitate the use of 2-D digital predistortion (2D-DPD) for linearization. In this brief, we discuss the 2D-DPD of a class $E/F_{\mathrm{odd}}$ PA-based Cartesian RF-power-digital to analog converter (DAC) transmitter. The effects of parameters associated with the 2D-DPD such as the rotation of the static nonlinearity constellation, size of predistortion look-up tables (LUTs), and interpolation technique on system performance metrics such as error vector magnitude (EVM) and output power are discussed. We also investigate design tradeoffs related to output power, efficiency, and the effective number of bits in such transmitters. This brief is supported by measurement results from a watt-level 2.4-GHz 9-b Cartesian RF-power-DAC transmitter implemented in 65-nm CMOS.