An 11b 300MS/s 0.24pJ/conversion-step Double-Sampling Pipelined ADC with on-chip full digital calibration for all nonidealities including memory effects

An 11b Double-Sampling Pipelined ADC (DS-PADC) with memory effect calibration is presented. The full digital calibration simplifies the analog circuit, which extends the operation speed over 300MHz. The chip is fabricated in a 40nm CMOS and occupies 0.42mm 2 including the calibration logics. The ADC consumes 40mW from a 1.8V supply, and the FoM is 0.24pJ/conversion-step.