Application of a redefinable symbolic simulation technique in VLSI testability design rules checking

Symbolic simulation approach is well suited for VLSI design for testability rules checking. Unfortunately the existing techniques are not extensible and therefore the verification tools based on them can not face up to the evolution of rules. This paper discusses the need of this kind of method and then describes a new symbolic simulation in which symbolic information is separated from the simulation algorithm and considered as redefinable data to cope with the extension of rules and different design methodologies. >