Design methodology for chip-on-chip applications

Y.L. Low,R.C. Frye,K.J. O'Connor

Design methodology for chip-on-chip applications

1997

Y.L. Low
R.C. Frye
K.J. O'Connor

We describe a design methodology for several chip-on-chip applications that uses a single redistribution metal layer on each chip and solder bumps as vias to form a two-level routing system.

Keywords:

Physical design
Chip
ChIP-on-chip
Engineering
Integrated circuit design
Soldering
Electronic engineering
Circuit design
Routing (electronic design automation)
Integrated circuit packaging
Embedded system
Design methods

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