Two causes of source/drain series resistance in bottom-contact pentacene thin-film transistors

We identified two causes of source/drain (S/D) series resistance (Rs) in bottom-contact (BC) pentancene thin-film transistors (TFTs). One is mixed-phase pentacene grown in the blurred- edge region of Au electrodes and the other is the semi-insulating pentacene region between the Au electrode and the carrier-accumulating layer. A novel Au S/D electrode structure with a self-assembled monolayer (SAM) adhesion layer enables direct injection of carriers into the accumulating layer and markedly reduces Rs for unit gate width (RsW) to 6 MΩ µm. BC TFTs with this electrode structure showed extrinsic field-effect mobility as high as 1.1 cm2/Vs.