Reliable Design for Crossbar Nano-architectures

The conventional CMOS technology faces various challenges in the continues down-scaling. Therefore, different emerging technologies based on bottom-up and self-assembly nanofabrications are being explored to overcome these challenges. These technologies exploit different nano-materials in the regular structures such as the crossbar nano-architecture, which is a two-dimensional grid with configurable switches at the crosspoints. Exploiting nano-materials in crossbar nano-architectures offers the possibility of significantly denser circuits at reduced fabrication costs compared to the existing lithography-based manufacturing. However, in these nano-architectures atomic device sizes and poor control on the fabrication processes impairs the reliability of these circuits. In this chapter, we investigate reliability issues in crossbar nano-architectures in terms of variation and defect tolerance. We study two approaches, namely logic mapping and self-timed architecture design, to provide variation and defect tolerance. In the logic mapping approach, different configurations, a.k.a mappings, of a logic function on a crossbar nano-architecture are explored to find the configuration with the required variation and defect tolerance. Simulation results, on a set of benchmark circuits, show that the proposed logic mapping approach achieves variation tolerance more than 98% of the cases, while in 100% of the cases all defects are tolerated. The efficiency of these algorithms is independent of crossbar size. At the architecture-level, a self-timed nano-architecture is introduced to reduce the circuit vulnerability to delay variations. Compared to the synchronous counterparts, with around 50% overhead in the number of activated switches, the proposed architecture provides 100% tolerance of delay variations.