An ultra-low-power CMOS on-chip interconnect architecture

An ultra-low-power CMOS static on-chip interconnect architecture is proposed. It is based on using low-swing on the capacitive bus. The power due to the charging and discharging of the bus is reduced by a factor as high as 10 at 3.3 V without any delay degradation. The circuits are implemented in 0.8 /spl mu/m CMOS technology. The performance can be improved using multi-threshold voltage techniques without any increase in DC power.