Compiling for VLIWs and ILP

This chapter focuses on the optimizations, or code transformations, critical to compiling for ILP architectures. The style of this chapter is closest to that of textbooks on optimization and compilation. This chapter begins with profiling, collecting the statistics that drive many of the most important ILP optimizations, and many aspects of processor design. Even though many embedded applications can be considered “loop-oriented,” profiling can still indicate the hottest parts of the program and the related “trip count” information that many loop-oriented code transformations can use. It covers various aspects of instruction scheduling, including an overview of the many types of schedulers, region formation, acyclic schedule compaction, resource management, cyclic scheduling, and scheduling for clustered architectures. It continues with a section on register allocation, a topic that interacts closely with scheduling. The chapter discusses a variety of mechanisms for speculation, and the somewhat orthogonal technique of predication. Both of these techniques are used sparingly in embedded applications because of the power and complexity costs associated with their implementations. It ends with a discussion of instruction selection, which is especially important to processors (such as DSPs) with idiosyncratic instructions sets.