A submicrometer NMOS multiplexer-demultiplexer chip set for 622.08-Mb/s SONET applications

The development of a low-power 12-channel multiplexer-demultiplexer pair that is clocked at the standard synchronous optical network (SONET) rate of 622.08 MHz is discussed. Each device has been integrated in silicon using a 0.75- mu m NMOS VLSI technology that provides high fabrication yield at relatively low cost. Highlighted are the analog interface circuits of the two chips. These include a phase splitter and amplifier for the maser clock input, a precision 50- Omega output driver for high-speed synchronous-transport-signal-12 (STS-12) data, as well as input amplifier and an output stage for low-speed differential STS-1 data. >