An improved Quasi-Type-1 PLL based on paralleled filtering stage

Abstract In three-phase grid synchronization applications, the performance of traditional phase-locked loops will decrease under non-ideal grid voltage conditions. In order to solve the above problem, moving average filters (MAF) has been widely studied and utilized in PLLs in recently published papers with the expense of slower transient speed. This paper proposes a paralleled filtering stage to improve the dynamic performance of PLL. The suggested filter with smaller time delay is based on MAF and delay signal cancellation (DSC) operator, which is integrated in quasi-type-1 structure based PLL (QT1-PLL). Compared with differential MAF-PLL (DMAF-PLL) and QT1-PLL, the proposed filter can obtain a faster transient response without degrading phase estimation accuracy. The experimental results demonstrate that the proposed method can provide satisfactory performance.