A comprehensive packaging solution for next generation IC substrates

The requirements for reduction of line and space dimensions in IC substrates are driving developments to improve both production yield and capability. In particular the production of substrates with line and space dimension at or below 10 µm is required for the next level of integration. However traditional production techniques using dry film image transfer are already reaching capability limits and are unlikely to achieve satisfactory future production requirements especially considering the production process yield. This paper presents the latest developments in a system for the production of structures based on the copper filling of trenches on a dielectric substrate. The system is being targeted for the manufacture of IC package substrates with capability for sub 8 µm lines and spaces. The resulting package may be characterized by padless vias and shows significant electrical performance improvements in comparison to substrates produced using standard production methods. The trenches are produced by laser ablation of the dielectric which is subsequently metalized, this method of track embedding gives an improved circuit adhesion due to the three point contact to the substrate in comparison to the standard method of production, typically using the semi-additives process (SAP) where tracks are produced with contact only at the base. Recent optimization of the electrolytic copper plating process has resulted in an improved metal distribution and more uniform copper filling of the ablated trenches. The latest results in circuitisation are shown together with data on substrate capability using the trench filling technology.