Systematic power reduction and performance analysis of mismatch limited ADC designs

This paper focuses on several methods to save power consumption in mismatch limited ADC designs, like flash and folding architectures. Migrating existing designs to a next submicron technology helps to reduce the power consumption significantly. It is shown that decreasing bandwidth and sample rate creates a more than linear reduction of the power consumption. Both of these methods are addressed in this paper. Also the balance between power consumption of the analog and digital circuitry is examined. An existing 6-bit 1.6GS/s ADC in 0.18/spl mu/m CMOS is transferred to a 0.12/spl mu/m technology. The sampling rate is reduced to 260MS/s, the measured ERBW to 124MHz while running at only 32mW. As the bandwidth is downscaled 5/spl times/, the power consumption is reduced by 10/spl times/, which results in an improved conversion efficiency. As the design topology is unaltered, the implemented design sets a reference for evaluation of any low-power technique.