Error Rate Prediction of Applications Implemented in Multi-Core and Many-Core Processors

This work proposes an approach for predicting the error rate of applications implemented in multi/many-core processors. The prediction is based on the intrinsic sensitivity of the device and the soft error-rate of the application. This approach applies the principles of Code Emulating Upset (CEU) method, which combines radiation experiments with software-Implemented fault-injection. CEU approach has been demonstrated to be very effective for mono-core processors. However, advanced devices such as many-core processor implement complex architectures regarding memory hierarchy and communications. For this reason, an extension of the CEU technique is required to face these new features. In this chapter are explored three devices with different technologies and architectures aiming at providing a general approach for SEE evaluation and error-rate prediction. The target devices are: the Freescale P2041, Epiphany E16G301 and MPPA-256 multi/many-core processors. Obtained results provide relevant information about how to select an appropriate device depending on the application and the operating environment. In addition, it can be seen a small underestimation of the error rate since not all sensitive areas of the device could be targeted during fault injection campaigns.