Test circuit for propagation delay of triggers in FPGA (Field Programmable Gate Array)

The invention relates to a test circuit for the propagation delay of triggers in an FPGA (Field Programmable Gate Array). The test circuit comprises an oscillator enabling circuit, a tested asynchronous reset trigger chain and a reset signal selection circuit. In the invention, a test for the signal propagation delay of the triggers in the FPGA is carried out by structuring an annular oscillator; a series of triggers to be tested are contained in a loop of the oscillator; a cascade structure is particularly employed; the output end of each of the triggers is connected to the clock end of a next-stage trigger; an ascending edge or a descending edge generated at the output end is about to drive the next-stage trigger in the annular oscillator; a clock edge goes across the time sum of the triggers in the loop, namely, an oscillating cycle of the annular oscillator; the interference beyond the tested delay is reduced to the largest extent; the signal propagation delay of the output of the triggers in the FPGA relative to the clock edge can be measured more precisely; and a more precise parameter model is provided for the time sequence analysis applied by the FPGA.