A design-oriented approach for modeling integrators non-idealities in discrete-time sigma-delta modulators

This paper presents a new way of modeling the integrators non-idealities for high-level sigma-delta modulator models. In this way, designers can correlate directly the integrator specifications like finite DC gain, Gain-Bandwidth product and Slew Rate with modulator performances (SNR, SNDR). Taking into account capacitive effects, a high degree of accuracy is obtained which is verified by transistor level simulation results.