Low-Power and High-Throughput Architecture for 3D-HEVC Depth Modeling Mode 4

The 3D-High Efficiency Video Coding (3D-HEVC) is an extension of the High Efficiency Video Coding (HEVC) standard targeting 3D-video encoding. The use of this extension leads to a significant computational-effort increase since new tools are introduced to efficiently encode 3D videos. Therefore, the real-time processing of 3D-videos using 3D-HEVC is highly challenging, and it requires the development of efficient hardware solutions, mainly when mobile devices with energy constraints are considered. This paper focuses on the Depth Modeling Mode 4 (DMM4) encoding mode which is one of the novelties introduced by 3D-HEVC. A low-power and high-throughput architecture was designed and presented in this paper targeting the DMM4, and this architecture was synthesized targeting FPGA and ASIC. The FPGA synthesis was focused on an Altera Stratix V, and the ASIC synthesis was focused on the 45nm Nangate technology. The FPGA and ASIC results showed that the architecture can process UHD 2160p 3D-videos (two views) at 60 fps or to process five views of HD 1080p 3D-videos at 30 frames per second, surpassing the related works in area usage, power dissipation, and processing rate.