The reliability of through silicon via under thermal cycling

Through silicon via (TSV) is a critical element for three-dimensional (3D) integration of devices in vertically multilevel stack-die microelectronic packages. In this paper, the microstructure evolution of TSV-Cu under thermal cycling was studied and the topography of TSVs under thermal cycling tests was examined by white light interferometer. It was found that the Cu was intrude inside the Si die during the test, and the intrusion height increased with cycle time and leveled off at 0.72µm and 0.53µm for upside and backside after 210 cycles, respectively. Besides, the Cu intrusion height at the Cu/Si interface is greater than that in the middle of Cu bar. in addition, cracks were observed at SiO 2 /Ta barrier interface and between BEOL line and Cu vias. It suggests that diffusional creep of the interface is the key for Cu via intrusion, the residual stress and thermal stress drive the interfacial sliding at interfaces.