A Machine Learning Approach to Predict Timing Delays During FPGA Placement

Timing-driven placement tools for FPGAs rely on the availability of accurate delay estimates for nets in order to identify and optimize critical paths. In this paper, we propose a machine-learning framework for predicting net delay to reduce miscorrelation between placement and detailed-routing. Features relevant to timing delay are engineered based on characteristics of nets, available routing resources, and the behavior of the detailed router. Our results show an accuracy above 94%, and when integrated within an FPGA analytical placer Critical Path Delay (CPD) is improved by 10% on average compared to a static delay model.