High efficient pipeline design and implementation for sub-pixel interpolation process in H.264/AVC

A two-level pipeline architecture was proposed in order to decrease the high complexity of sub-pixel interpolation process in H.264/AVC decoding system.The first level pipeline scheme was utilized to explore the parallelism for the interpolation processes of different 4×4 blocks with two stages of fetching 4×4 block's reference pixels and interpolation computation operation when the four 4×4 blocks inside one 8×8 block share the same motion information.The second level pipeline scheme was used to accelerate the sub-pixel interpolation computation operation of different pixels by using the independence of adjacent half-pixels and the symmetry between horizontal and vertical interpolation computation processes.The kernel interpolation computation unit was implemented with 13 six-tap filters,4 bilinear interpolation filters and 4 chroma interpolation filters.The pipelining and parallelism in interpolation computation process can reduce computation time by at least 75%.Experimental results show that the proposed architecture design can reduce the external memory bandwidth by 47% and improve the performance of sub-pixel interpolation by 30% at a lower hardware cost compared with other designs.