Compact Spiking Neural Network Implementation in FPGA

An FPGA based Artificial Neural Network is proposed. The neuron is based on a spiking scheme where signals are encoded in a stochastic pulse train. The neuron is composed of a synaptic module and a summing-activation module. The architecture of the neuron is characterized and its FPGA implementation is presented. The basic spiking neuron is used to implement a basic neural network. An extension of the neuron architecture to include an address-event protocol for signal multiplexing in a single line is proposed. VHDL simulations and FPGA synthesis results are discussed.