Integrated semiconductor memory with adjusting the rating behavior of sense amplifiers

Integrated semiconductor memory with adjusting the rating behavior of sense amplifiers - an output terminal (DQ) for outputting a datum (D), - having memory cells (SZ1, SZ2), each having a function of a memory state of a cell voltage (Vwrite) - to bit line pairs (BLP1, BLP2) which each comprise a first and a second bit line (BLT, BLC, BLT ', BLC), - sense amplifiers (SA1, SA2) each rate the cell voltage of one of the memory cells, - wherein said first memory cell (SZ1) via one of the bit lines (BLT) of a first said bit line pairs (BLP1) are connected to a first sense amplifier (SA1), - in which the second memory cell (SZ2) via one of the bit lines (BLT ') of a second bit line pairs (BLP2) with a second sense amplifier (SA2) are connected, - is wherein the first sense amplifier (SA1) is constructed such that it during a read access to one of the first memory cell (SZ1), the cell voltage (Vwrite) of the one ...