Simulation of serpentine trace of DQ PCB layout for DDR3 applications

This paper presents an analysis of a simulated serpentine signal line for a DDR3 memory interface. DDR implementation on a PCB should allow for the estimation of the figure except for the DQ length and impedance matching. To match the DQ timing specification in a PCB (printed circuit board), a serpentine line is simulated using an EM (electromagnetic) tool and DOE (design of experiments) analysis. In the same manner, the weight of a serpentine structure is quantified by comparing it with the other factors of PCB routing. The simulated factors prioritize the design of a memory interface in a system.