Mitigating Aperture Error in Pipelined ADCs Without a Front-end Sample-and-Hold Amplfier

Pipelined analog-to-digital converters (ADCs) without dedicated front-end sample-and-hold amplifier (SHA) suffer from aperture-error. This error is caused by the mismatch in the sampled signal between the sub-ADC and the multiplying digital-to-analog converter (MDAC) of the first stage. This paper describes a newarchitecture that eliminates this aperture-error. A 12-bit pipelined ADC was designed and simulated in UMC 65-nm SP process with the first stage being replaced by the proposed architecture. Simulations show that the performance of the proposed architecture is same as that of the conventional architecture provided the conventional architecture does not have any aperture-error.