Templated Si-based Nanowires via Solid-Liquidsolid (SLS) and Vapor-Liquid-Solid (VLS) Growth: Novel Growth Mode, Synthesis, Morphology Control, Characteristics, and Electrical Transport

The ‘scaling down’ of device and interconnect features in CMOS technology to the deep sub100 nm regime has motivated substantial research focusing on the development of nanoscale building blocks formed via self-assembled or ‘bottom-up’ synthesis to complement prevailing lithographic or ‘top-down’ CMOS processing. Examples of such nanoscale building blocks include metallic and semiconducting nanowires or nanobelts, carbon nanotubes and, most recently, n-layer graphenes. In particular, one-dimensional (1D) nanostructures have attracted much attention because of their unique electrical, optical, mechanical and thermal properties and their potential utility in a wide variety of nanoelectronic and optoelectronic applications. Non-carbon 1-D nanomaterials fabricated from bottom-up synthesis can be used as fundamental building blocks for nanoscale devices and circuits and may have the potential to replace certain, conventional top-down processes. In particular, silicon nanowires (SiNWs) may be an attractive alternative to conventionally processed Si transistors if their intrinsic self-assembly can be harnessed to obviate the need for complex lithographic techniques for device fabrication. In addition, SiNWs can potentially function as both the switch (i.e. transistor) and local interconnect (e.g. metal silicide nanowire) to form an inherently integrated nanoelectronic system – potentially on the same self-assembled nanostructure (Morales et al. 1998; Lu et al. 2007; Colli et al. 2007; Wu et al. 2004). Recent research has demonstrated that Si-based silicide nanowires may yield performance superior to conventional Cu interconnects at sub 10-nm wire widths which highlights the excellent potential for SiNW-based systems (Wu et al. 2004; Zhang et al. 2000; Kim et al. 2005; Kim et al. 2003). And since NiSi has been shown to be a good electrical contact material for gate, source and drain in Si CMOS (Lavoie et al. 2003; Kittl et al. 2003; Morimoto et al. 1995), NiSi nanowires, in particular, comprise an attractive nanoscale building block material (Wu et al. 2004). Currently, several methods are available to synthesize silicon nanowires including laser ablation (Morales et al. 1998; Zhang et al. 1998), physical vapor deposition (Zakharov et al. 8