A 2-D amplifier array chip for pixel detector readout

Abstract A 32 × 16 array of 200 × 200 μm 2 pixel amplifier cells has been fabricated using 1.5 μm CMOS technology. Each pixel contains charge amplification and noise filtering, a comparator and a one-bit latch. A fast readout scheme incorporating zero suppression has been designed. Amplifier array chips can be interconnected and “tiled” onto the surface of a large area pixel detector using the bump-bonding technique. The measured performance of the individual pixel amplifiers is presented, and the operation of the readout circuitry is described. The noise dependence on input capacitance is 125+0.33/fF rms electrons. For the anticipated detector capacitance noise levels of less than 200 rms electrons can be expected. Silicon hybrid pixel detectors can be used for applications in synchrotron X-ray, autoradiography and high energy particle detection.