Increasing the Ride-Through Fault Capability of a Power Electronics-Based Arc-Flash Suppressor

In this paper it is proposed and analyzed the design of a current-limiting impedance for a power-electronics based arc-flash suppressor presented in a previous work, which is a solution intended for arcing fault elimination in switchgears and motor control centers of industrial and commercial facilities. The objective is that the surge current through the electronic switch and power system is reduced still guaranteeing that the arcing fault is safely eliminated, ensuring safety to nearby workers and preserving equipment. A complete computational model for the system is implemented in ATP Draw based on experimental low-voltage arcing fault waveforms provided by the IEEE-NFPA working group, experimentally obtained equivalent model of power system, and the dynamic model of a commercially available thyristor. A computational analysis is made and fundamental guidelines for the specification of the current-limiting impedance are presented, which is the main contribution of this work.