A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias

In a speed-adaptive threshold-voltage CMOS (SA-V/sub t/ CMOS) scheme, the substrate bias is controlled so that delay in a circuit remains constant. The substrate bias is continuously changed from -1.5 V of reverse bias to 0.5 V of forward bias in order to compensate for fabrication-process fluctuation, supply-voltage variation, and operating-temperature variation. Advantages and disadvantages of substrate bias control with the forward bias are discussed. The SA-Vt CMOS scheme with forward bias is implemented in a 4.3M-transistor microprocessor. The controller occupies 320/spl times/400 /spl mu/m in area and consumes 4-mA current. A 0.5-V forward bias raises the maximum operating frequency of the processor by 10%. The processor provides 400 VAX MIPS at 1.5-1.8 V supply with 320-380-mW power dissipation, that is, it achieves 1.2-GIPS/W performance.