A method for manufacturing a nonvolatile memory device having a self-aligned gate structure

A method for manufacturing a nonvolatile memory device, comprising: Forming a tunnel dielectric layer (210) on a semiconductor substrate (100); Forming first floating gate patterns (300) on the tunnel dielectric layer (210); Forming shape patterns (400) on the first floating gate patterns (300), to selectively expose predetermined portions of the first floating gate pattern (300); Forming floating gate (300 ') by removing the exposed portions of the first floating gate pattern (300) using the shape pattern (400) as a mask; Forming an interlayer dielectric layer pattern (500) (300 ') for insulating the floating gates from each other by filling gaps between the mold patterns; Removing the mold pattern (400) that have been exposed between the interlayer dielectric layer patterns (500), using the interlayer dielectric layer pattern (500) as an etch mask; Forming a dielectric layer (250) on the floating gates (300 ') caused by the removal of the mold pattern (400) between the interlayer dielectric layer patterns (500) have been exposed; and Forming control gates (600) connected to the floating gates (300 ') are aligned, ...