HW/SW Co-design of TA/SPA-resistant Public-key Cryptosystems

This paper proposes a hardware/software (HW/SW) co-design methodology for secure Public-Key Cryptosystems. Our design flow allows to assess the risk for simple side-channel attacks including Timing Analysis (TA) and Simple Power Analysis (SPA) at an early design stage. It also allows to evaluate the quality of countermeasures against these attacks. The HW/SW co-design is illustrated with an Elliptic Curve Cryptosystem (ECC) over GF(p). By balancing the execution time in SW and HW, a first order sidechannel-resistant design can be obtained with a 15% increase in latency for a point multiplication.