A multi-way set-associative cache memory in which an output is selected by selecting one of the sense amplifiers

The disclosure is a multi-way set associative cache memory with a set selection signal operating a sense amplifier. In reading data stored in a set, a set selection signal enables a sense amplifier to select one of sets while plural sets are active by a row address. The simplified structure of the present cache memory reduces power consumption by the rate of 1/N (N is the number of sets).