Down literal circuit with neuron-MOS transistors and its applications

A voltage-mode neuron-MOS(/spl nu/MOS) down literal circuit which realizes an arbitrary down literal function is proposed. It provides the benefit that the circuit can be easily fabricated by standard CMOS process, instead of the multi-level ion implantation applied in the conventional circuit. It has a variable threshold voltage by way of controlling only two bias voltages. Its noise margin and switching sensitivity are greater than those of variable-threshold C-VMOS inverter presented by Shibata. The threshold voltage errors of the circuit caused by device parameters mismatch is also analysed. Using the /spl nu/MOS down literal circuits, literal and T-gate circuits are also presented. Performances of the proposed circuits are evaluated using HSPICE simulations with MOSIS 2.0 /spl mu/m CMOS device parameters.