Temporal signal-to-noise ratio of a CMOS buried double junction image sensor

This paper presents an accurate temporal noise analysis of a new kind of CMOS image sensor for colour design. Operating in the charge storage mode, the noise of this APS is described with a time-varying model. During the reset phase, as the steady state is fast established, classical frequency-domain noise analysis can still be used to determine noise at both sensing nodes. Good agreement is observed between the results obtained by simulation with Cadence CAD tools of a 0.35μm-CMOS test structure and the behaviour predicted by the proposed analytical approach. During the integration phase, as both junctions are floating, the stationary state condition is never fulfilled and the noise analysis must be carried out in the time-domain. Our contribution consists in taking into account the non-linearity of the junction capacitance, which yields more realistic results. Considering only the dominant white noise component, it clearly appears that the junction non-linearity improves the output SNR for both sense nodes at high illumination and/or high integration period.