DSP algorithms to optimised ASICs-an automated route

Design automation tools that support DSP designers to develop and explore DSP algorithms have been successfully used for many years. They provide the most productive route to commercial DSP processors but, to date, have not provided an automatic route to ASICs that yields the level of optimisation needed to implement, effectively, the arithmetic intensive functionality of DSP applications. This paper outlines a newly developed route to bridge the gap between a proven DSP design environment and one of the most productive complex ASIC design environments for standard cell, gate array and FPGA implementations. The key to providing a successful solution to this missing link between DSP algorithm development and optimal ASIC implementations hinges on the use of a mix of advanced synthesis and datapath compiler technology. It utilises a comprehensive library of datapath elements such as adders, multipliers and storage elements that have pre-built structures at both the ASIC gate and highly optimised layout level. This interface takes an automatically generated behavioural VHDL description of the fixed-point signal flow graph and creates a hierarchical datapath specification schematic and associated control logic. To demonstrate the effectiveness of this route a design example starting from a DSP signal flow graph through to standard-cell, gate-array and FPGA structures is detailed.